1. Field of the Invention
The present invention relates generally to a semiconductor package and, more particularly, to a chip stack structure having a plurality of vertically stacked semiconductor chips, and to a system-in-package (SIP) module using the chip stack structure.
A claim of priority is made to Korean Patent Application No. 2005-102526, filed on Oct. 28, 2005, the entire contents of which are incorporated herein by reference.
2. Description of the Related Art
There has been an increase in demand for portable products that require light, thin, and small semiconductor packages functioning as components mounted in these portable products. To cope with this demand, there have been various technology-oriented efforts in the semiconductor packaging industry. For example, one approach attempts to reduce sizes of individual semiconductor packages. Another approach includes using a system-on-chip (SOC) technology for integrating multiple components together in a chip. Yet another approach includes a system-in-package (SIP) technology for integrating multiple semiconductor chips in a package.
The SIP technology permits multiple semiconductor chips to be vertically or horizontally mounted in a package. Furthermore, the SIP technology may be regarded as an extension of a conventional multi-chip module (MCM) technology. While multiple semiconductor chips are normally mounted in a horizontal manner in the MCM technology, they are normally mounted in a vertical manner in the SIP technology.
FIG. 1 represents a prior art SIP module 10. Referring to FIG. 1, SIP module 10 includes two or more stacked semiconductor chips. If a lower chip (a first chip 12) is larger than an upper chip (a second chip 14), the second chip 14 may be directly stacked on the first chip 12. The first chip 12 may be electrically connected to a wiring substrate 11 through first bonding wires 13 and the second chip 14 may be electrically connected to the wiring substrate 11 through second bonding wires 15. The first chip 12 mounted on an upper surface of the wiring substrate 11, the second chip 14, and the first and second bonding wires 13 and 15 may be protected by a molding compound 16. Furthermore, solder balls 17 may be formed at a lower surface of the wiring substrate 11.
In the SIP module 10 having the chip stack structure described above, the first chip 12 and second chip 14 may not be shielded from each other. In addition, the first and second bonding wires 13 and 15 may be formed close to each other. Consequently, signal interference may occur between signals transferred via the first bonding wires 13 and signals transferred via the second bonding wires 15. This signal interference may degrade the performance of the SIP module 10.
When the second chip has a size greater than or similar to that of the first chip, then, as disclosed in U.S. Pat. No. 5,323,060, there is a need for a spacer between the first and second chips. As shown in FIG. 2, in a SIP module 20 having such a chip stack structure, the spacer 28 acts to suppress electrical interference caused by mechanical contact between first bonding wires 23 connected to a first chip 22 and the lower surface of a second chip 24.
In the SIP module 20, the first chip 22 and second chip 24 are not shielded from each other, and the first bonding wires 23 are exposed to the second chip 24. Consequently, performance of the SIP module 20 may be degraded owing to signal interference between the first chip 22 and second chip 24. In particular, this signal interference may become serious if a semiconductor chip sensitive to external electromagnetic fields, such as, for example, a radio frequency (RF) device, is stacked in the SIP module 20.
When an RF device is stacked in a SIP module, the RF device may be stacked before a baseband device according to the chip stack structure of FIG. 2. That is, the RF device is used as the first chip 22, and the baseband device is used as the second chip 24. Therefore, there is a need to solve problems caused by the signal interference between the RF and baseband devices.
In addition, a portion of the second chip 24 at which second electrode pads 24a are formed is configured in an overhang structure. This overhang structure is not supported by the first chip 22. The lack of support for the overhang structure may affect the wire bonding. For example, in a wire bonding operation, cracks may develop at edge portions of the second chip 24 or the bonding quality of second bonding wires 25 may be degraded. These problems may become more serious with a decrease in thickness of the second chip 24 and an increase in width of the overhang structure. Specifically, in a wire bonding operation for connecting the second chip 24 to a wiring substrate 21, a capillary may apply a predetermined amount of force to the second chip 24 to bond one end of each second bonding wire 25 to a second electrode pad 24a. In particular, when the portion at which the second electrode pads 24a are formed is not supported at the lower part thereof, and is thin, cracks may develop at the edge portions of the second chip 24 because of the force applied by the capillary. Furthermore, when the edge portions of the second chip 24 vibrate owing to a reaction force caused by the action force of the capillary, the quality of bonds between the second electrode pads 24a and second bonding wires 25 may be lowered.
The present disclosure is directed to overcoming one or more of the problems associated with the prior art SIP modules.